// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  vpc_pipe_nmanager_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/19 14:39:47 Create file
// ******************************************************************************

#ifndef __VPC_PIPE_NMANAGER_REG_OFFSET_H__
#define __VPC_PIPE_NMANAGER_REG_OFFSET_H__

/* VPC_PIPE_NMANAGER Base address of Module's Register */
#define SOC_VPC_PIPE_NMANAGER_BASE                       (0x5000)

/******************************************************************************/
/*                      SOC VPC_PIPE_NMANAGER Registers' Definitions                            */
/******************************************************************************/

#define SOC_VPC_PIPE_NMANAGER_IN_SWAP_REG         (SOC_VPC_PIPE_NMANAGER_BASE + 0x0)  /* Input data swap */
#define SOC_VPC_PIPE_NMANAGER_RGB2YUV_1_REG       (SOC_VPC_PIPE_NMANAGER_BASE + 0x4)  /* rgb to yuv coeffcient */
#define SOC_VPC_PIPE_NMANAGER_RGB2YUV_2_REG       (SOC_VPC_PIPE_NMANAGER_BASE + 0x8)  /* rgb to yuv coeffcient */
#define SOC_VPC_PIPE_NMANAGER_RGB2YUV_3_REG       (SOC_VPC_PIPE_NMANAGER_BASE + 0xC)  /* rgb to yuv coeffcient */
#define SOC_VPC_PIPE_NMANAGER_RGB2YUV_4_REG       (SOC_VPC_PIPE_NMANAGER_BASE + 0x10) /* rgb to yuv coeffcient */
#define SOC_VPC_PIPE_NMANAGER_RGB2YUV_5_REG       (SOC_VPC_PIPE_NMANAGER_BASE + 0x14) /* rgb to yuv coeffcient */
#define SOC_VPC_PIPE_NMANAGER_RGB2YUV_6_REG       (SOC_VPC_PIPE_NMANAGER_BASE + 0x18) /* rgb to yuv coeffcient */
#define SOC_VPC_PIPE_NMANAGER_UVDEC_1_REG         (SOC_VPC_PIPE_NMANAGER_BASE + 0x1C) /* uv dec filter parameter */
#define SOC_VPC_PIPE_NMANAGER_UVDEC_2_REG         (SOC_VPC_PIPE_NMANAGER_BASE + 0x20) /* uv dec filter parameter */
#define SOC_VPC_PIPE_NMANAGER_UVDEC_3_REG         (SOC_VPC_PIPE_NMANAGER_BASE + 0x24) /* uv dec filter parameter */
#define SOC_VPC_PIPE_NMANAGER_PRECROP_1_REG       (SOC_VPC_PIPE_NMANAGER_BASE + 0x28) /* pre-crop horizontal position */
#define SOC_VPC_PIPE_NMANAGER_PRECROP_2_REG       (SOC_VPC_PIPE_NMANAGER_BASE + 0x2C) /* pre-crop vertical position */
#define SOC_VPC_PIPE_NMANAGER_POSTCROP1_1_REG     (SOC_VPC_PIPE_NMANAGER_BASE + 0x30) /* post-crop 1 horizontal position */
#define SOC_VPC_PIPE_NMANAGER_POSTCROP1_2_REG     (SOC_VPC_PIPE_NMANAGER_BASE + 0x34) /* post-crop 1 vertical position */
#define SOC_VPC_PIPE_NMANAGER_POSTCROP2_1_REG     (SOC_VPC_PIPE_NMANAGER_BASE + 0x38) /* post-crop 2 horizontal position */
#define SOC_VPC_PIPE_NMANAGER_POSTCROP2_2_REG     (SOC_VPC_PIPE_NMANAGER_BASE + 0x3C) /* post-crop 2 vertical position */
#define SOC_VPC_PIPE_NMANAGER_PIPE_CTRL_REG       (SOC_VPC_PIPE_NMANAGER_BASE + 0x40) /* vpc pipeline control */
#define SOC_VPC_PIPE_NMANAGER_PIPE_INFOR_1_REG    (SOC_VPC_PIPE_NMANAGER_BASE + 0x44) /* vpc pipeline vp bus information */
#define SOC_VPC_PIPE_NMANAGER_PIPE_INFOR_2_REG    (SOC_VPC_PIPE_NMANAGER_BASE + 0x48) /* vpc pipeline vp bus information */
#define SOC_VPC_PIPE_NMANAGER_PIPE_INFOR_3_REG    (SOC_VPC_PIPE_NMANAGER_BASE + 0x4C) /* vpc pipeline vp bus information */
#define SOC_VPC_PIPE_NMANAGER_PIPE_BUSY_INFOR_REG (SOC_VPC_PIPE_NMANAGER_BASE + 0x50) /* vpc pipeline busy information */
#define SOC_VPC_PIPE_NMANAGER_Y_SUM_REG           (SOC_VPC_PIPE_NMANAGER_BASE + 0x54) /* vpc main output (ai core) y summary */
#define SOC_VPC_PIPE_NMANAGER_U_SUM_REG           (SOC_VPC_PIPE_NMANAGER_BASE + 0x58) /* vpc main output (ai core) u summary */
#define SOC_VPC_PIPE_NMANAGER_V_SUM_REG           (SOC_VPC_PIPE_NMANAGER_BASE + 0x5C) /* vpc main output (ai core) v summary */

#endif // __VPC_PIPE_NMANAGER_REG_OFFSET_H__
